1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to an integrated circuit utilizing the design for testability to efficiently check an internal logic circuit thereof.
2. Description of the Related Art
In recent years, the integration density of a logic circuit has been more enhanced as the semiconductor integrated circuit technology has been more developed. The large scale integration of the logic circuit produces various advantages such as the enhancement of the function of the logic circuit and reduction in the weight thereof, but at the same time, the large scale integration makes it extremely difficult to execute the test of the logic circuit itself and create test data for the test. As a result, a design which is made by taking the test into consideration, or a so-called design for testability has been gradually used at the design stage of the logic circuit.
In the conventional design for testability a method called a scan design system and a method of adding a compact test system called a self-test circuit have been generally used and these methods are described below.
As shown in FIG. 1, the scan design system is a method to directly set the data state of flip-flop (FF) circuits 74 to 76 of the logic circuit in the integrated circuit from the exterior of the integrated circuit by effecting the scan-in operation using the shift register, input the thus set data to a combinational circuit 73 by use of the system clock, operate the entire portion of the LSI, output the data state of the combinational circuit 73 to the flip-flop circuits 74 to 76, and then scan out the same via the shift register so that the internal state of the combinational circuit 73 can be checked and thus the defect checking test of the combinational circuit 73 can be simplified. In other words, the test of the sequential circuit is replaced by the test of the combinational circuit by regarding the input and output terminals of the flip-flop circuits 74 to 76 as the external terminals of the integrated circuit. Therefore, if the scan design system is used, a test vector can be automatically generated based on the connection in the logic circuit.
However, the above scan design system has a disadvantage that a large amount of hardware must be added, and at the time of test, time for the scan-in and scan-out may become excessively long depending on the number of stages of the flip-flop circuits, thereby making the entire test time longer.
A semiconductor integrated circuit in which the scan-in and scan-out operations can be effected in a short period of time with a simple circuit construction and with a slight increase in the number of input and output pins in a case where the internal logic circuit is divided into multiple blocks and it is desired to effect the test for each block is proposed in Japanese Patent Application No. 62-78551 (Japanese Patent Disclosure No. 63-243890) which was filed before the present application and made by the same inventor of the present application.
As shown in FIG. 2, the compact test system is a method to generate a test vector by use of a pseudo-random number generator 81 which is represented by a linear feedback shift register (LFSR) having a feedback loop in which an exclusive OR gate is provided, for example, input the thus generated test vector to a logic circuit 82, compress an output signal from the logic circuit 82 by means of a data compressor 83, and then compare the compression result with an expected value so as to check whether the circuit is defective or not.
The compact test system is advantageous over the scan design system in that an amount of added hardware can be reduced but is not suitable for analysis of the defect.
Further, the basic construction of a method called a BILBO (Built-In Logic Block Observation) system which is a combination of the scan design system and the compact test system is shown in FIG. 3. The construction includes a feedback loop containing a multiplexer 91, flip-flop (FF) circuits 92 to 95 and an exclusive OR gate 96, and groups of gate circuits 971 to 974, 981 to 984 and 991 to 994. The operation mode of the BILBO system includes four modes of a reset mode for resetting the flip-flop circuits 92 to 95, a normal latch mode for effecting the normal operation of the flip-flop circuits 92 to 95, a scan pass mode for effecting the scanning operation of the flip-flop circuits 92 to 95, and an LFSR mode for effecting the pseudo-random number generating operation by using the flip-flop circuits 92 to 95 as a linear feedback shift register by use of the feedback loop, and various tests for the logic circuit can be made.
However, the above BILBO system has a disadvantage that it will depend on the mathematical method such as irreducible polynomials when the number of stages of the LFSR for effecting the pseudo-random number generating operation is large.